THE QUANTUM INTELLIGENCER

Fast, Bias-Preserving CZ Gate for Dual-Rail Erasure Qubits In Plain English: Quantum computers are powerful but fragile—tiny errors can ruin calculations. This research tackles that by designing a special kind of quantum bit (qubit) where most errors can be spotted and fixed easily. The team built a fast connection (a 'gate') between two of these special qubits, showing it works reliably and keeps the error-correcting advantage. Because the most common errors are detectable, like a missing signal, future quantum computers could correct mistakes much more efficiently. This makes building large, stable quantum computers more achievable in the near future. Summary: The paper presents the design and experimental realization of a two-qubit entangling gate—specifically a controlled-Z (CZ) gate—for dual-rail cavity qubits, a promising type of erasure qubit in superconducting circuits. Erasure qubits are engineered so that the most common errors, such as photon loss, are detectable, effectively turning them into 'erasure errors' that are easier to correct than random errors. This property allows quantum error correction (QEC) codes to tolerate higher physical error rates and achieve better scaling. However, for this advantage to hold, all operations—including two-qubit gates—must preserve the error hierarchy, with erasures dominating over residual Pauli errors. Until now, such a gate was missing for dual-rail cavity qubits, despite their excellent single-qubit performance and erasure detection capabilities. The authors introduce the 'Swap–Wait–Swap' (SWS) gate, a fast (~500 ns) CZ operation that uses a transmon coupler to mediate interaction between two dual-rail qubits. The gate works by temporarily swapping a photon from one cavity of the control qubit to the coupler, leveraging the dispersive shift between the coupler and a cavity of the target qubit to generate entanglement. After a controlled wait time, the photon is swapped back, completing the gate. This design avoids populating any mode with more than one photon, preventing self-Kerr effects and preserving the excitation number, which ensures that photon loss leads to detectable erasures rather than undetectable errors. The gate is bias-preserving: erasure rates are low (~0.5% per gate), residual dephasing errors are below 0.1%, and bit-flip errors are suppressed to the 10⁻⁶ level, maintaining the favorable noise structure crucial for QEC. The team benchmarks the gate using quantum state tomography (QST) and interleaved randomized benchmarking (IRB). Starting with Bell state generation, they achieve a post-selected state fidelity of 99.60(1)% after one gate, with infidelity attributed to SPAM, single-qubit gates, and the CZ gate. Repeated gate sequences up to N=103 show a post-selected infidelity of 0.12(1)% per gate, among the best for superconducting qubits. IRB yields a consistent error estimate of 0.108(5)%. Erasure asymmetry is observed: the control qubit suffers higher erasure (0.400%) and dephasing (0.039%) than the target (0.096% and 0.0112%), due to the coupler’s lower coherence. Bit-flip errors remain negligible. Crucially, the gate exhibits benign leakage propagation: if a qubit leaks to vacuum, subsequent CZ gates are effectively skipped, allowing delayed erasure checks in QEC without degrading performance. Quantum process tomography confirms that leakage from the |01⟩ state results in a conditional dephasing error on the target qubit, which is still correctable. Simulations using Stim show that this error model enables high logical error suppression in the surface code, with a suppression factor Λ ≈ 27—nearly double that of depolarizing noise (Λ ≈ 14). Delayed erasure checks at the end of syndrome rounds are viable, preserving threshold (~5.6%) and code distance scaling (α ≈ 0.93). The authors conclude that the SWS gate completes the operational toolbox for dual-rail cavity qubits and opens a viable path to fault-tolerant quantum computing with significantly reduced overhead. Key Points: - The 'Swap–Wait–Swap' (SWS) gate is a fast (~500 ns) CZ entangling gate for dual-rail cavity qubits that preserves the erasure-to-Pauli error hierarchy. - Erasure rates are low (~0.5% per gate), residual Pauli errors are below 0.1%, and bit-flip errors are suppressed to ~10⁻⁶, making errors highly structured and correctable. - The control qubit experiences higher erasure and dephasing due to coupler decoherence, but this asymmetry can be managed in QEC protocols. - Leakage during the gate causes subsequent CZ operations to be skipped, enabling delayed erasure checks in quantum error correction without loss of threshold or code distance. - Surface code simulations show a logical error suppression factor Λ ≈ 27, nearly double that of depolarizing noise, due to the structured error model. - Bell state fidelity reaches 99.60(1)% post-selection, and repeated gate benchmarking yields a CZ error of 0.12(1)% per gate. - The gate avoids multi-photon states, preventing self-Kerr errors and preserving excitation number, which ensures photon loss leads to detectable erasures. - This work completes the gate set for dual-rail cavity qubits, enabling scalable, fault-tolerant quantum computing with reduced overhead. Notable Quotes: - "Our experimental demonstration confirms that the error hierarchy is largely preserved during the gate." - "The gate is fast (about 500 ns duration) and shows low erasure rates of approximately 0.5% per gate, remaining Pauli errors below 0.1%, and a strong bias towards dephasing errors, in which bit-flips are practically non-existent at the 10⁻⁶ level." - "These results enable a faster path to error-corrected systems that rapidly suppress errors as they scale." - "Once a qubit has leaked to |00⟩, subsequent CZ gates are skipped, which allows us to perform less frequent erasure checks." - "We find that even with current CZ gate performance, the error rates are already a factor of ten below the respective erasure and dephasing thresholds." Data Points: - CZ gate duration: ~500 ns - Total erasure probability per CZ gate: 0.53(2)% - Post-selected infidelity per CZ gate: 0.12(1)% (from N=103 gates) - IRB error per CZ gate: 0.108(5)% - Bell state fidelity (post-selected): 99.60(1)% - Control qubit erasure rate: 0.400(4)% per gate - Target qubit erasure rate: 0.096(4)% per gate - Control qubit Z error: 0.039(1)% per gate - Target qubit Z error: 0.0112(9)% per gate - Bit-flip error rate: bounded at a few parts per million per gate (~10⁻⁶) - Logical error suppression factor Λ: ≈27 (structured noise) vs ≈14 (depolarizing) - Surface code threshold with delayed checks: 5.6% - Scaling exponent α: 0.93 (close to ideal 1 for erasures) - Coupler dispersive shift χ_bc/2π: −1.51 MHz - Parametric coupling g_ac/2π: 4.23 MHz Controversial Claims: - The claim that delayed erasure checks (at the end of syndrome rounds) do not degrade threshold or code distance may challenge conventional QEC practices that require frequent mid-circuit checks. - The assertion that bit-flip errors are at the 10⁻⁶ level suggests near-ideal noise bias, which may be difficult to maintain in larger systems or under realistic noise conditions. - The simulation-based claim of Λ ≈ 27 for logical error suppression assumes idealized conditions (e.g., perfect erasure checks), which may not hold in practical implementations. - The paper implies that dual-rail cavity qubits are on a faster path to fault tolerance than other platforms, a strong comparative claim that depends on future scalability and integration. - The patent filing by several authors introduces potential bias in the presentation of results as uniquely enabling for fault tolerance. Technical Terms: - Dual-rail qubit: A qubit encoded in two physical modes (e.g., cavities), where information is stored in the presence of a single excitation in one mode or the other. - Erasure qubit: A qubit engineered so that dominant errors are detectable (e.g., photon loss), enabling more efficient quantum error correction. - Controlled-Z (CZ) gate: A two-qubit quantum gate that applies a π phase shift only when both qubits are in the |1⟩ state. - Swap–Wait–Swap (SWS) gate: A specific implementation of a CZ gate using parametric swaps and a dispersive interaction mediated by a coupler. - Quantum state tomography (QST): A method to reconstruct the density matrix of a quantum state through repeated measurements in different bases. - Interleaved randomized benchmarking (IRB): A protocol to estimate the error rate of a specific gate by interleaving it within random sequences. - Dephasing (Z) error: A quantum error that affects the phase of a superposition state without changing the bit value. - Bit-flip (X) error: A quantum error that changes the |0⟩ state to |1⟩ or vice versa. - Surface code: A leading quantum error correction code that arranges qubits in a 2D lattice to detect and correct errors. - Logical error suppression factor (Λ): The factor by which the logical error rate decreases when the code distance increases by two. —Ada H. Pemberley Dispatch from The Prepared E0