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Density-Preserving Single-Transistor Memory Encryption Using Ferroelectric FET Technology In Plain English: This research solves a fundamental problem in computer memory: how to keep stored information secure without reducing the amount of data you can store. The researchers created a new way to encrypt memory that uses special transistors that can remember their state even when powered off. Unlike previous methods that required extra hardware and slowed things down, their approach works within the existing memory structure. This matters because it enables faster, more secure computing for everything from smartphones to AI systems, allowing them to process sensitive data efficiently without compromising storage capacity. Summary: This paper presents a novel approach to encrypting non-volatile memories that eliminates the density penalty typically associated with hardware encryption. The researchers developed a single-transistor encryption cell using ferroelectric FET (FeFET) technology that encodes ciphertext in the device's threshold voltage. This innovation removes the requirement for two memory devices per encrypted cell that characterized previous XOR-based schemes, allowing encrypted memory arrays to maintain the same storage density as unencrypted arrays. The key technical insight leverages the direction-dependent current flow of FeFETs for single-cycle decryption, which also eliminates the need for two write cycles, enabling faster encryption operations. The approach extends to multi-level-cell FeFETs capable of storing multiple bits per transistor. Validation through simulation and experimental evaluation demonstrates significant performance improvements: a 128x128-bit array achieves 2x higher encryption/decryption throughput than prior FeFET work and 45.2x/14.12x improvement over AES encryption. Application-level testing using neural network benchmarks shows average latency reductions of 50% compared to prior FeFET-based schemes and 95% compared to AES-based approaches. Key Points: - First single-transistor encrypted cell that eliminates the two-device requirement in XOR-based encryption schemes - Maintains full storage density while providing encryption capabilities - Uses FeFET threshold voltage encoding for ciphertext storage - Leverages direction-dependent current flow for single-cycle decryption - Extends to multi-level-cell configurations for higher density - 2x higher throughput than prior FeFET encryption work - 45.2x encryption and 14.12x decryption improvement over AES - 50% latency reduction vs prior FeFET schemes, 95% vs AES in neural network applications Notable Quotes: - "To our knowledge, [this] is the first to eliminate the two-memory-devices-per-encrypted-cell requirement in XOR-based schemes, enabling encrypted memory arrays to maintain the same number of storage devices as unencrypted arrays." - "The key idea is an in-memory single-FeFET XOR scheme, where the ciphertext is encoded in the device threshold voltage and leverages the direction-dependent current flow of the FeFET for single-cycle decryption." Data Points: - 128x128-bit array used for performance evaluation - 2x higher encryption/decryption throughput than prior FeFET work - 45.2x improvement over AES encryption - 14.12x improvement over AES decryption - 50% average latency reduction compared to prior FeFET-based schemes - 95% average latency reduction compared to AES-based schemes - Neural network benchmarks used for application-level evaluation Controversial Claims: - The paper claims this is the "first" approach to eliminate the two-device requirement, which may be contested if similar concepts exist in unpublished work or adjacent fields. The dramatic performance improvements over AES (45.2x/14.12x) represent strong claims that would require independent verification, particularly given AES's established security properties versus the proposed lightweight XOR approach. Technical Terms: - Non-volatile memories (NVMs) - Ferroelectric FET (FeFET) - Advanced Encryption Standard (AES) - XOR-based encryption - Threshold voltage - Direction-dependent current flow - Multi-level-cell (MLC) - Encryption/decryption throughput - Single-cycle decryption - Ciphertext encoding —Ada H. Pemberley Dispatch from Trigger Phase E0