THE QUANTUM INTELLIGENCER

A paper has been laid before the arXiv repository under the title Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices. It describes an accelerator reported to be the first complete implementation of the Falcon signature scheme written directly in a hardware description language, rather than assembled from partial designs or generated through high-level synthesis. Falcon, one of the schemes standardized by the National Institute of Standards and Technology, carries the most compact signatures and public keys of the standardized candidates; its reliance on floating-point arithmetic has made full hardware implementation difficult. The authors report a design for resource-constrained edge devices that lack a native floating-point unit, using an emulated floating-point datapath. Placed on a single Artix 7 XC7A200T FPGA, the Falcon-1024 variant uses 85,261 lookup tables, 41,382 flip-flops, 44 block RAMs and 142 DSP slices. Measured against FalconTakesOff, the only prior full implementation, the design uses 1.9 times fewer lookup tables, 3.4 times fewer flip-flops, 2.7 times fewer block RAMs and 9.9 times fewer DSP slices; it fits on one FPGA where the earlier design required at least two. Operated as a peripheral to an on-chip MicroBlaze soft-core, the accelerator is said to reduce the clock cycles required for key-pair generation, signature generation and signature verification by 92, 96 and 85 per cent, respectively, relative to an emulated floating-point reference software. These figures are the authors'; independent inspection of the hardware has not yet been reported. The substance of the paper, once the acceleration figures are set aside, is a statement about fit. Falcon's compact signatures make it the standardized scheme one would want at the edge; its floating-point arithmetic is why it has not been there. Peregrino answers that objection with an emulated floating-point datapath, allowing a device without a native floating-point unit to run key-pair generation, signature generation, and signature verification from a soft-core peripheral on a single Artix 7 FPGA. The resource counts matter less than the arrangement: this is not a partial accelerator for one operation, but the complete scheme. For a migration plan, the relevant point is therefore not that the hardware is fast. Speed is negotiable. The point is that Falcon no longer has to be excluded from edge hardware on floating-point grounds alone. Whether the paper's figures survive independent measurement remains open, and the authors' comparison to prior work is not yet corroborated. For the record, the entry reads: complete Falcon, one FPGA, no native floating-point unit, reported by the authors. —Inspector Grey Dispatch from The Prepared E0